1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More specifically, the present invention relates to an MOS (metal oxide semiconductor) type semiconductor device and a complementary MOS (CMOS) type semiconductor device, and a method for fabricating the same.
2. Description of the Related Art
In recent years, in pursuit of a higher integration of a VLSI (very large scale integrated circuit), an MOS type semiconductor device used for such a VLSI has been increasingly miniaturized. At present, there is realized a device having a channel length as small as half a micron. As the device is miniaturized, however, the electric characteristics of the device may be degraded by hot carriers. This brings a serious problem with regard to the reliability of the device.
In order to minimize the degradation of the device caused by hot carriers and moreover to improve the device characteristics such as transconductance, a gate-drain overlap LDD (lightly doped drain) structure has been proposed. Examples of such a structure includes an ITLDD structure proposed in T. Y. Hung, "IEEE 1986 IEDM", Technical Digest, pp. 742-745 and a GOLD structure proposed in R. Izawa, "IEEE Transaction on Electron Devices", vol. 35, pp. 2088-2093, 1988.
Referring to FIG. 16, an MOS transistor having the gate-drain overlap LDD structure will be described.
The transistor includes n-type high-concentration source/drain diffusion regions 33 and n-type low-concentration diffusion regions 34 both of which are formed in a p-type semiconductor substrate 31, a gate oxide film 32 formed on a portion of the semiconductor substrate 31, a gate electrode 35 formed on the gate oxide film 32, and gate side walls 36 formed on both sides of the gate electrode 35. The high-concentration source/drain diffusion regions 33 extend to reach a portion beneath the ends of the gate electrode 35. The low-concentration diffusion regions 34 are entirely located beneath the gate electrode 35. With this structure, the electric field generated laterally in the low-concentration diffusion regions 34 is weakened by a potential applied to the gate electrode 35 enough to reduce the generation of hot carriers. Moreover, carriers in the low-concentration diffusion regions 34 can be completely controlled by the gate electrode 35, and the source resistance at the low-concentration diffusion regions 34 is reduced. As a result, the drivability of the device improves.
However, the gate-drain overlap LDD structure has problems when they are applied to an MOS transistor having a channel length of a half-micron or less as follows:
(1) Since the low-concentration diffusion regions 34 are entirely located beneath the gate electrode 35, the effective channel length L.sub.eff has a following relationship: EQU L.sub.eff &lt;L.sub.g -2.times.L.sub.ldd
wherein L.sub.g is the gate length and L.sub.ldd is the width of the low-concentration diffusion regions 34 (measured in the channel direction).
The width L.sub.ldd of the low-concentration diffusion regions 34 requires at least 0.1 .mu.m. Therefore, for an MOS transistor with the gate-drain overlap LDD structure, the effective channel length L.sub.eff is shorter than the gate length L.sub.g by at least 0.2 .mu.m. When the channel length of the transistor is half a micron or less, the effective channel length L.sub.eff is as small as 0.3 .mu.m or less. As a result, the infant degradation of the characteristics of the device generally caused when the channel thereof is shorter (short channel effects) becomes more eminent, compared with the case of an LDD structure.
(2) Since the low-concentration diffusion regions 34 are entirely located beneath the gate electrode 35, the drivability of the transistor improves. However, this results in the increase in the gate-to-drain capacitance. This significantly lowers the driving characteristics of a circuit including the MOS transistor.
(3) When the thickness of the gate oxide film 32 is 10 nm or less, a tunnel current is induced between the energy bands, which may become an additional cause of a leak current.
(4) At least two masking steps are required for forming the low-concentration diffusion regions 34 and the high-concentration source/drain diffusion regions 33. For a CMOS circuit, a total of four or more masking steps are required including similar masking steps for forming a p-channel MOS transistor.
For the above reasons, favorable transistor characteristics will not be obtained if the gate-drain overlap structure is applied to an MOS transistor having a channel length of half a micron or less. Moreover, when it is applied to a CMOS circuit, the entire fabricating process thereof will be further complicated.
Now, problems of an MOS type semiconductor device with the LDD structure will be described as follows by showing the fabricating process thereof with reference to FIGS. 17A to 17C:
As shown in FIG. 17A, impurities of a second conductivity type such as phosphorus (P) ions are implanted into a surface area of a semiconductor substrate 31 using a gate electrode 35 as a mask, thereby forming the low-concentration diffusion regions 34. Thereafter, as shown in FIG. 17B, an oxide film is first deposited on the semiconductor substrate 31 covering the gate electrode 35 to a thickness of approximately 200-250 nm. Then, the oxide film is removed by anisotropic dry etching except portions thereof deposited on the sides of the gate electrode 35. At this etching, since the width of the oxide film left unetched on the sides of the gate electrode 35, i.e., gate side walls 36 greatly depends on the conditions of the etching, it is difficult to form the gate side walls 36 with high accuracy. Therefore, when the width of the resultant gate side walls 36 formed on the sides of the gate electrode 35 is large as shown in FIG. 17C, the high-concentration source/drain diffusion regions 33 formed by the diffusion of implanted impurities of a second conductivity type such as As ions do not extend to reach a portion beneath the gate electrode 35.
As a result, following problems arise:
(1) Though the short channel effects become less significant, the generation of hot carriers increases, compared with the case of the gate-drain overlap LDD structure.
(2) Though the gate-to-drain capacitance decreases, the drivability of the device decreases.
(3) At least two masking steps are required for forming the low-concentration diffusion regions 34 and the high-concentration source/drain diffusion regions 33. For a CMOS circuit, a total of four or more masking steps are required including similar masking steps for forming a p-channel MOS transistor.